1. Technical Field
This invention relates generally to memory devices, and more particularly, to a memory structure incorporating memory-diodes.
2. Background Art
Generally, memory devices associated with computers and other electronic devices are employed to store and maintain information for the operation thereof. Typically, such a memory device includes an array of memory cells, wherein each memory cell can be accessed for programming, erasing, and reading thereof. Each memory cell maintains information in an “off” state or an “on” state, also referred to as “0” and “1” respectively, which can be read during the reading step of that memory cell.
As such electronic devices continue to be developed and improved, the amount of information required to be stored and maintained continues to increase. FIG. 1 illustrates a type of memory cell known as a memory-diode 30, which includes advantageous characteristics for meeting these needs. The memory-diode 30 includes, for example, an electrode 32, a superionic layer 34 on the electrode 32, an active layer 36 on the superionic layer 34, and an electrode 38 on the active layer 36. Initially, assuming that the memory-diode 30 is unprogrammed, in order to program the memory-diode 30, a negative voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30 (see FIG. 2, a plot of memory-diode current vs. electrical potential applied across the memory-diode 30). This potential is sufficient to cause copper ions to be attracted from the superionic layer the 34 toward the electrode 38 and into the active layer 36 (A), causing the active layer 36 (and the overall memory-diode 30) to be in a (forward) low-resistance or conductive state. Upon removal of such potential (B), the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory-diode 30) remain in a conductive or low-resistance state.
FIG. 3 illustrates the read step of the memory-diode 30 in its programmed (conductive) state. An electrical potential Vr (the “read” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30. This electrical potential is sufficient to overcome the threshold voltage Vt of the inherent diode characteristic of the memory-diode 30, but is less than the electrical potential Vpg applied across the memory-diode 30 for programming (see above). In this situation, the memory-diode 30 will readily conduct current, which indicates that the memory-diode 30 is in its programmed state.
In order to erase the memory-diode (FIG. 4), a positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the reverse direction of the memory-diode 30. This potential is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34, causing the active layer 36 (and the overall memory-diode 30) to be in a high-resistance or substantially non-conductive state (see FIG. 5, illustrating application of electrical potential Ver across the memory-diode 30). This state remains upon removal of such potential from the memory-diode 30.
FIG. 6 illustrates the read step of the memory-diode 30 in its erased (substantially non-conductive) state. The electrical potential Vr is again applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30, as described above. With the active layer 34 (and memory-diode 30) in a high-resistance or substantially non-conductive state, the memory-diode 30 will not conduct significant current, which indicates that the memory-diode 30 is in its erased state.
As will be seen, the memory-diode as thus far shown and described is capable of adopting two states, i.e., a first, conductive state, or “on” state, and a second, substantially non-conductive, or “off” state. Each memory-diode thus can include information as to the state of a single bit, i.e., either 0 or 1. However, it would be highly desirable to be able to provide a memory-diode which is capable of adopting each of a plurality of states, so that, for example, in the case where four different states of the memory-diode can be adopted, two bits of information can be provided as chosen (for example first state equals 00, second stage equals 01, third state equals 10, fourth state equals 11).
Therefore, what is needed is an approach wherein a memory-diode may adopt each of a plurality of states, each relating to the information held thereby.